The present invention relates to semiconductor devices, and more particularly to a method of fabricating a semiconductor structure that includes a carbon and oxygen containing monolayer between a first material layer such as, for example, a first semiconductor layer and any other film, such as, for example, a second semiconductor layer, that overlays the first material layer. This monolayer can serve as a barrier to dopant diffusion during subsequent thermal processing.
Controlling dopant diffusion is highly desirable in the fabrication of semiconductor devices. Nontraditional metal oxide semiconductor field effect transistors (MOSFETs), such as super steep retrograde well devices, require that the high dose well dopants remain in the ground plane and do not diffuse into the undoped channel regions. Even conventional p-MOSFETs require that boron in the gate electrode does not penetrate the gate dielectric.
Diffusion is traditionally limited in the prior art by minimizing the thermal cycles during processing. Despite its use to limit diffusion, this prior art approach limits the flexibility of the process integration.
Additionally, diffusion is minimized in some prior art processes by growing a film atop a semiconductor layer to retard dopant diffusion. An example of this prior art approach is the growth of a SiC film atop a semiconductor layer. The SiC film has been shown to minimize boron diffusion. The technique of growing a film atop a semiconductor layer to minimize dopant diffusion can add additional challenges to the semiconductor manufacturer, such as, for example, the need for modifying the dry etching processes for heterogeneous stacks that will now include the dopant diffusion minimizing film.
Another prior art method for minimizing dopant diffusion includes co-implantation of a diffusion retarding element into a semiconductor layer. This prior art approach however is also problematic since the co-implanted element would be distributed throughout the semiconductor layer, instead of being confined to an interface.
Some examples of prior art methods to control dopant diffusion include:
I. U.S. Pat. No. 5,731,626 to Eagelsham, et al. provides a process for controlling the diffusion of ion-implanted dopant atoms in a semiconductor layer. In accordance with the method disclosed in Eagelsham, et al., the diffusion of ion-implanted dopant atoms in a deposited semiconductor layer is controlled by incorporating a diffusion-suppressing amount of an electrically inactive impurity in the semiconductor layer by a crystal growth technique. The electrically inactive impurity is any atom or molecule which, when introduced to a semiconductor layer, will not interfere with the electrical properties of the semiconductor. One example of an electrically inactive impurity in the Eagelsham, et al. disclosure is substitutional carbon.
II. U.S. Pat. No. 5,967,794 to Kodama discloses a method of fabricating a semiconductor device with a shallow (on the order of 50 nm) PN junction depth. In the '794 disclosure, a silicon layer containing a substance such as carbon which combines with point defects in the semiconductor substrate is grown atop the substrate to prevent an impurity from diffusing.
III. U.S. Pat. No. 6,271,551 to Schmitz, et al. retards dopant diffusion by providing a thin layer of Si1-xGex between a strongly doped layer and an intrinsic surface region.
Despite the above advances in the art for minimizing dopant diffusion, there is still a need for a new and improved method whereby dopant diffusion can be substantially retarded, which does not require significant modifications to existing semiconductor processing techniques and does not disrupt the alignment of an overlying film to the lattice of a semiconductor substrate.